1. Field of the Invention
The present invention relates to a cell structure for a low electric power memory device, and in particular to a cell structure for a low electric power static RAM.
2. Background of the Related Art
As shown in FIG. 1, a related art low electric power static RAM (SRAM) includes a cell 1 having access NMOS transistors NM1 and NM3, the gates of which are connected with a word line and the sources of which are connected with a bit line, and drive NMOS transistors NM2 and NM4, the gates of which are connected with the drains of the access NMOS transistors NM1 and NM3 and the drains of which are connected with a ground voltage. The cell 1 of a load resistance static RAM also has load resistors RL1 and RL2 connected with the sources of the drive NMOS transistors NM2 and NM4. A step down voltage generator 2 applies a cell voltage VCE to the cell 1, and a standby mode detector 3 detects the mode of the step down voltage generator 2.
The operation of the related art cell structure for a low electric power static RAM (SRAM) will now be described. First, in the standby mode, if the word line is set at a low level, the access NMOS transistors NM1 and NM3 are turned off, and the drive NMOS transistors NM2 and NM4 are turned on or turned off. At this time, the cell voltage VCE is applied to the cell node via the resistors RL1 and RL2, and the current flows to the ground voltage VSS by the turn-on current of the drive NMOS transistors. The current flowing to the ground VSS through the load resistors RL1 and RL2 and the drive NMOS transistors NM2 and NM4 is called a standby current.
In addition, if the cell voltage VCE is a step down voltage VSD, the step down voltage generator 2 is driven by the standby mode detector 3, and the cell voltage VCE is decreased, which decreases the standby current of the cell.
In the retention mode, if the word line is set at a low level, the access NMOS transistors NM1 and NM3 are turned off, and the drive NMOS transistors NM2 and NM4 are turned on or turned off. The data retention voltage VDR, which is a battery backup voltage lower than 2.0V, flows to the cell voltage node via the load resistors RL1 and RL2 as a cell voltage VCE. At the same time, the leakage current of the drive NMOS transistors NM2 and NM4 of the cell flows to the ground by the leakage current.
As described above, the related art SRAM has various disadvantages. If the leakage current flowing via the drive NMOS transistors NM2 and NM4 is higher than the current from the load resistors RL1 and RL2, the high node voltage of the cell is decreased, and the data of the cell may be varied due to the cell characteristic of a latch type static RAM (SRAM). In addition, since there is no control circuit for the data retention mode and the signal is set at a high level in the data retention mode, the standby mode detector 3 is operated, and the cell voltage VCE is decreased to the step down voltage VSD, thereby deteriorating the data retention voltage characteristic of the cell.
In the related art cell structure of the static RAM (SRAM), since there is a cell voltage VCC applied to the memory cell in the standby mode, if the resistance values of the load resistors RL1 and RL2 are decreased during the processes, the standby current may be sharply increased. If the resistance values of the load resistors RL1 and RL2 are increased to decrease the standby current, the width and thickness are decreased based on the characteristic of the load poly forming the load resistors RL1 and RL2. In this case, the load resistors RL1 and RL2 may be open and may cause a low yield. Further, if the resistance values of the load resistors RL1 and RL2 are too high, the current flow to the cell voltage VCE via the load resistors RL1 and RL2 is decreased, and the characteristic of the data retention voltage may deteriorate. In addition, since there is no data retention control circuit, the cell voltage VCE is decreased in the retention mode for thereby deteriorating the characteristic of the data retention voltage.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.